The present invention relates to integrated circuit devices and methods of fabricating the same, and more particularly to, memory devices and methods of manufacturing the same.
A semiconductor memory device, such as dynamic random access memory (DRAM), static random access memory (SRAM) or non-volatile memory, typically includes a plurality of word lines, a plurality of bit lines, and a plurality of switching elements for switching signals between them. As is well known, a word line is a line used to select the switching element, and a bit line is a line that acts as an external signal line and transfers an external signal to the switching element when the switching element is turned on.
For example, as shown in FIG. 1, a unit cell of a conventional DRAM includes a word line WL, a bit line BL perpendicular to the word line WL, and a MOS transistor Tr. The MOS transistor Tr has a gate connected to the word line WL, a drain (or source) connected to the bit line BL, and a source (or drain) connected to a capacitor C, one terminal of which is connected to a signal ground.
As shown in FIG. 2, a unit cell of a conventional SRAM includes first and second inverters INV1 and INV2 configured as a latch, and access transistors TA1 and TA2 that transfer input signals to the first and second inverters INV1 and INV2. The first access transistor TA1 has a gate connected to a word line WL, a source (or drain) connected to a bit line BL, and a drain (or source) connected to an output terminal S1 of the first inverter INV1. The second access transistor TA2 has a gate connected to the word line WL, a source connected to a bit line bar (complementary bit line) DBL, and a drain connected to an output terminal S2 of the second inverter INV2. Here, a signal having a phase opposite to a bit line (BL) signal is applied to the bit line bar (DBL). In addition, the inverters INV1 and INV2 are configured with pull-up elements (PMOS transistors) and drive transistors (NMOS transistors). In addition to the PMOS transistor, a thin film transistor and a resistor can be used as the pull-up element. The above-described SRAM is described in U.S. Pat. No. 5,654,915.
As shown in FIG. 3, a unit cell of a conventional non-volatile memory device includes a word line WL, a bit line BL perpendicular to the word line WL, and a memory cell M connected between the word line WL and the bit line BL. The memory cell M has a gate connected to the word line WL, a drain connected to the bit line BL, and a source connected to a source electrode line S in common with another memory cell M. Such a non-volatile memory device is described in Japanese Patent Laid-open Publication No. 2000-179840.
Commonly, in such conventional memory devices, a plurality of transistors or memory cells is connected to one word line and one bit line. However, as semiconductor memory devices have become more highly integrated, line widths of the word line and the bit line have generally decreased, which can increase line resistance. Operating speed has also generally increased. As is well known, operating speed is generally a product of resistance R and capacitance C. Because resistance has generally reached a critical minimum value, recent attempts to improve speed have been directed to reducing parasitic capacitance.
Parasitic capacitance typically occurs where lines overlap. In particular, parasitic capacitance of bit lines often significantly influences the operating speed of a semiconductor memory device. The capacitance of a bit line may be viewed at the sum of a capacitance between the bit line and a substrate, a capacitance between the bit line (or a contact plug contacted with the bit line) and a word line, a capacitance between bit lines, and a junction capacitance occurring in a source or drain region of a silicon substrate to which the bit line (or the contact plug contacted with the bit line) is electrically connected. Among them, the parasitic capacitance between the bit line (or the contact plug contacted with the bit line) and the word line contributes to the total bit line loading capacitance.
FIG. 4 is a sectional diagram of a conventional DRAM, showing a word line and a contact plug for connecting to a bit line. Referring to FIG. 4, word line structures 20 are arranged on a semiconductor substrate 10 and spaced apart from each other a predetermined distance. Each of the word line structures 20 has a stacked structure including a gate oxide layer 12, a conductive layer 14 and a hard mask layer 16. Spacers (not shown) are typically formed of the same insulating layer on both sides of the word line structure 20. Source and drain regions 22a and 22b are formed on both sides of the word line structure 20, and contact plugs 25a and 25b are formed between the word line structures 20, in contact with respective ones of the source and drain regions 22a and 22b. 
A parasitic capacitance occurs in regions 30 and 31 in which the word line structures, especially the conductive layers 14, overlap the contact plugs 25a and 25b. This capacitance (hereinafter, referred to as a first capacitance) between the contact plug 25a and the word line structure 20 can increase a data storage capacitance, which can increase the cell stability. A subsequently formed storage node electrode contacts the contact plug 25a. The capacitance (hereinafter, referred to as a second capacitance) between the contact plug 25b and the word line structure 20 acts as a bit line loading capacitance, which can lower the speed characteristic of the cell. A subsequently formed bit line contacts the contact plug 25b. 
Generally, it is desirable for the first capacitance between the contact plug 25a and the word line structure 20 to be increased and for the second capacitance between the contact plug 25b and the word line structure 20 to be decreased. However, the first and second capacitances typically are substantially the same, because the conductive layers 14 of the word line structure 20 are formed with a uniform thickness and the spacers are also formed with a uniform thickness. Thus, it may be difficult to decrease the second capacitance while increasing the first capacitance in a conventional configuration.